1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device and, more particularly, to a method of fabricating a cell of a flash memory device.
2. Description of the Related Art
A flash memory device, among semiconductor memory devices, retains information stored in its memory cells even when no power is supplied. Accordingly, it has been used in various applications such as a flash memory card. A memory cell in which floating gate and control gate electrodes are sequentially stacked has been prevalently adopted as a unit cell of the flash memory device.
FIG. 1 is a cross-section of a unit cell of a conventional flash memory device.
Referring to FIG. 1, a source region S and a drain region D, isolated from each other and having a channel region therebetween, are formed on the surface of a semiconductor substrate 1, e.g., a p-type silicon substrate. The source and drain regions S and D are formed of a film doped with impurities of a different conductive type from the semiconductor substrate 1, i.e., an N.sup.+ -type impurity film. A thin tunnel oxide film 3 of 100 .ANG. or less, a floating gate (FG), a dielectric film 5, and a control gate (CG) electrode are sequentially formed on the channel region.
The unit cell of FIG. 1 is programmed by applying a voltage of 5V to 7V to the drain region D and a voltage of 10V to 12V to the control gate electrode CG. At this time, 0V is applied to the source region S and the semiconductor substrate 1. When appropriate voltages are applied to the control gate electrode CG, the source region S, the drain region D and the semiconductor substrate 1 to program the unit cell as described above, hot carriers generated by the channel region, i.e., channel hot electrons, pass through the tunnel oxide film 3 and are injected into the floating gate FG. Consequently, the programming is accomplished by increasing a threshold voltage of the unit cell shown in FIG. 1.
Also, an erasure operation is performed by grounding the control gate electrode CG and the semiconductor substrate 1 and applying a high voltage of between 12V and 15V to the source region S. At this time, the drain region D is floated. When appropriate voltages are applied to the control gate electrode CG, the source region S, the drain region D and the semiconductor substrate 1 to erase the information stored in the unit cell as described above, electrons, stored in the floating gate FG, pass through the tunnel oxide film 3 and reach the source region S because of the voltage difference between the floating gate FG and the source region S. Accordingly, all of the electrons in the floating gate FG are removed. Consequently, the erasure operation is accomplished while allowing the unit cell to have an initial threshold voltage or less.
FIG. 2 is an equivalent circuit diagram illustrating a capacitive coupling ratio of the unit cell shown in FIG. 1.
Referring to FIG. 2, a capacitance C.sub.ipo caused by the dielectric film 5 of FIG. 1 exists between the control gate electrode CG and the floating gate FG, and a capacitance C.sub.ch caused by the tunnel oxide film 3 of FIG. 1 exists between the floating gate FG and the semiconductor substrate 1, i.e., the channel region. Also, a capacitance C.sub.s caused by the tunnel oxide film 3 of FIG. 1 exists between the floating gate FG and the source region S, and a capacitance C.sub.d caused by the tunnel oxide film 3 of FIG. 1 exists between the floating gate FG and the drain region D. When a voltage V.sub.CG and a voltage V.sub.d 0 are applied respectively to the control gate electrode CG and the drain region D, and 0V is applied to both the source region S and the semiconductor substrate 1, in order to program the unit cell, a voltage V.sub.FG1 induced to the floating gate FG is expressed by the following Equation 1: EQU V.sub.FGI =[C.sub.ipo .div.(C.sub.ipo +C.sub.d +C.sub.ch +C.sub.s)].times.V.sub.CG
Also, when the control gate electrode CG and the semiconductor substrate 1 are grounded and a voltage V.sub.S is applied to the source region S with the drain region D floated, in order to erase information stored in the unit cell of FIGS. 1 and 2, a voltage V.sub.FG2 induced to the floating gate FG is expressed by the following Equation 2: EQU V.sub.FG2 =[C.sub.s .div.(C.sub.ch +C.sub.ipo +C.sub.s)].times.V.sub.s
It can be seen from Equations 1 and 2 that program efficiency and erase efficiency are increased by increasing the capacitance C.sub.ipo. This is because the voltage V.sub.FG1 induced to the floating gate FG during programming approaches the control gate voltage V.sub.CG and the voltage V.sub.FG2 induced to the floating gate FG during erasing approaches a ground potential, with an increase in capacitance C.sub.ipo. Thus, the capacitance C.sub.ipo between the floating gate and the control gate electrode must be increased to improve the characteristics of the unit cell of the flash memory device.
FIG. 3 is an equivalent circuit diagram of a portion of a cell array region of a conventional NOR-type flash memory device adopting the unit cell of FIG. 1.
Referring to FIG. 3, a plurality of bit lines B/L1, B/L2 are parallel to each other, and a plurality of unit cells are connected respectively to the bit lines. Also, a plurality of word lines W/L1 and W/L2 cross the plurality of bit lines B/L1 and B/L2, and each word line is electrically connected to the control gate electrode of the unit cell. Here, a pair of cells connected to one bit line in parallel share one source region. The source region is connected to a common source line C/S which is parallel to the word lines.
In order to program a cell C1 of FIG. 3, a program voltage, e.g., a voltage between 10V and 12V, is applied to the first word line W/L1, and a voltage between 5V and 7V is applied to the first bit line B/L1. Also, the second word line W/L2 and the common source line C/S are grounded. Here, when the cell C1 is selected from the cells C1 and C2 sharing the first bit line B/L1 and then programmed, a voltage V.sub.FG3 induced to the floating gate of the cell C2 is expressed by the following Equation 3: EQU V.sub.FG3 =[C.sub.d .div.(C.sub.ch +C.sub.ipo +C.sub.s C.sub.d)].times.V.sub.d
wherein V.sub.d denotes a voltage applied to a drain region of the cell C2, i.e., a voltage applied to the first bit line B/L1.
As can be seen from Equation 3, when the cell C1 is programmed, the voltage V.sub.FG3 is induced to the floating gate of the cell C2. V.sub.FG 3 is proportional to the drain voltage V.sub.d, and approaches the drain voltage V.sub.d as the capacitance C.sub.ipo becomes small. Accordingly, when the capacitance C.sub.ipo decreases, the unselected cell C2 is turned on and disturbs the programming on the selected cell C1, which is called a drain turn-on phenomenon. As a result, in order to increase programming efficiency of a desired cell, the drain turn-on phenomenon must be suppressed by increasing the capacitance C.sub.ipo.
FIG. 4 is a layout view of a portion of a cell array region to realize the equivalent circuit diagram shown in FIG. 3.
Referring to FIG. 4, a plurality of word line patterns 15 are parallel to each other, and an active region pattern 11 crosses the word line patterns 15. A common source region pattern S extending from the active region pattern 11 is disposed in parallel to and between the word line patterns 15. The active region pattern 11, opposing the common source region pattern S having the word line pattern 15 therebetween, corresponds to a drain region D of a cell. A bit line contact pattern 17 is disposed in each of the drain regions D, and a bit line pattern 19 covering the bit line contact pattern 17 is perpendicular to the word line pattern 15. Also, an etch mask pattern 13, for isolating the floating gates of adjacent cells in the direction of the word line patterns 15, is placed between the bit line patterns 19.
FIGS. 5 through 8 are cross-sections of FIG. 4 taken along line B-B', illustrating a method of fabricating a cell of a flash memory device disclosed in U.S. Pat. No. 5,675,162.
Referring to FIG. 5, a field oxide film 23 for defining active and inactive regions is formed in a predetermined region of a semiconductor substrate 21. A tunnel oxide film 25 is formed on the surface of the active region. A first doped polysilicon film 27 and a silicon nitride film 29 are sequentially formed on the entire surface of the semiconductor substrate on which the tunnel oxide film 25 is formed. A photoresist pattern 31 is formed on the silicon nitride film 29, using a photomask on which the etch mask pattern 13 of FIG. 4 is drawn.
Referring to FIG. 6, the silicon nitride film 29 is etched until the first doped polysilicon film 27 is exposed, using the photoresist pattern 31 as an etch mask, thereby forming a silicon nitride film pattern 29 covering the upper portion of the active region. A second doped polysilicon film 33 is formed on the entire surface of the semiconductor substrate on which the silicon nitride film pattern 29 is formed.
Referring to FIG. 7, a spacer 33' is formed on the sidewalls of the silicon nitride film pattern 29 by anisotropically etching the second doped polysilicon film 33. Then, the first doped polysilicon film 27 is etched by using the silicon nitride film pattern 29 as an etch mask, thus forming a first doped polysilicon film pattern 27.
Referring to FIG. 8, the first doped polysilicon film pattern 27 is exposed by removing the silicon nitride film pattern 29. Then, an insulating film 35, such as an oxide/nitride/oxide (O/N/O) film, and a third polysilicon film 37 are sequentially formed on the entire surface of the semiconductor substrate from which the silicon nitride film pattern 29 has been removed. The third polysilicon film 37, the insulating film 35, and the first doped polysilicon film pattern 27 are continuously etched by using a photomask on which the word line pattern 15 of FIG. 4 is drawn, thereby forming a floating gate 27 and a control gate electrode 37.
In the above-described U.S. Pat. No. 5,675,162, the gap between adjacent floating gates is made smaller than a resolution limit of photolithography, to maximize the area where a floating gate overlaps with a control gate electrode. Also, a spacer formed of a second doped polysilicon film remains on the edge of the floating gate. Accordingly, the capacitance between the floating gate and the control gate electrode can be maximized. However, according to the U.S. Pat. No. 5,675,162, when a high voltage is applied to the control gate electrode, a strong electrical field is concentrated between the spacer and the control gate electrode since the spacer has sharp upper edges. Hence, the reliability and breakdown voltage of an insulating film interposed between the floating gate and the control gate electrode are degraded.